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general description the max6323/max6324 microprocessor (?) supervi- sory circuits monitor power supplies and ? activity in digital systems. a watchdog timer looks for activity out- side an expected window of operation. six laser- trimmed reset thresholds are available with ?.5% accuracy from +2.32v to +4.63v. valid reset output is guaranteed down to v cc = +1.2v. the reset output is either push-pull (max6323) or open-drain (max6324). reset is asserted low when v cc falls below the reset threshold, or when the manual reset input ( mr ) is asserted low. reset remains assert- ed for at least 100ms after v cc rises above the reset threshold or mr is deasserted. the watchdog pulse output ( wdpo ) utilizes an open- drain configuration. it can be triggered either by a fast timeout fault (watchdog input pulses are too close to each other) or a slow timeout fault (no watchdog input pulse is observed within the timeout period). the watchdog timeout is measured from the last falling edge of watchdog input (wdi) with a minimum pulse width of 300ns. wdpo is asserted for 1ms when a fault is observed. eight laser-trimmed timeout periods are available. the max6323/max6324 are offered in a 6-pin sot23 package and operate over the extended temperature range (-40? to +125?). applications automotive industrial medical embedded control systems features min/max (windowed) watchdog, 8 factory-trimmed timing options pulsed open-drain, active-low watchdog output power-on reset precision monitoring of +2.5v, +3.0v, +3.3v, and +5.0v power supplies open-drain or push-pull reset outputs low-power operation (23a typ) debounced manual reset input guaranteed reset valid to v cc = +1.2v max6323/max6324 ? supervisory circuits with windowed (min/max) watchdog and manual reset ________________________________________________________________ maxim integrated products 1 gnd v cc wdi 16 5 max6323 max6324 sot23 top view 2 34 reset mr wdpo 19-1838; rev 1; 1/01 *these devices are factory trimmed to one of eight watchdog- timeout windows and one of six reset voltage thresholds. insert the letter corresponding to the desired watchdog-timeout window (a, b, c, d, e, f, g, or h) into the blank following the number 6323 or 6324 (see watchdog timeout table). insert the two-digit code (46, 44, 31, 29, 26, or 23) after the letters ut for the desired nominal reset threshold (see reset threshold range table at end of data sheet). note: there are eight standard versions of each device available (see standard versions table). sample stock is generally held on standard versions only. standard versions have an order incre- ment requirement of 2500 pieces. nonstandard versions have an order increment requirement of 10,000 pieces. contact factory for availability of nonstandard versions. pin configuration ordering information typical operating circuit appears at end of data sheet. reset output pin- package temp. range part * max6323 _ut_ _-t -40? to +125? 6 so t23-6 push-pull open drain 6 sot23-6 -40? to +125? max6324 _ut_ _-t watchdog timeout* suffix a b c d e f g h 719 39 23 15 15 15 15 1.5 max fast units ms ms ms ms ms ms ms ms slow min units ms 10 100 300 10 60 s ms 47 82 1.3 s * see figure 1 for operation. for price, delivery, and to place orders, please contact maxim distribution at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. watchdog timeout
max6323/max6324 ? supervisory circuits with windowed (min/max) watchdog and manual reset 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v cc = full range, t a = -40? to +125?, unless otherwise noted. typical values are at v cc = 3v, t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. terminal voltage (with respect to gnd) v cc ..................................................................-0.3v to +6.0v mr , reset (max6323), wdi .............-0.3v to (v cc + +0.3v) wdpo , reset (max6324) ..............................-0.3v to +6.0v input current, v cc , wdi, mr ..............................................20ma output current, reset , wdpo ..........................................20ma rate of rise, v cc ............................................................100v/? continuous power dissipation (t a = +70?) 6-pin sot23 (derate 8.7mw/? above +70?) ..........696mw operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol min typ max units 4.25 4.38 4.50 4.50 4.63 4.75 supply current i cc 27 57 ? operating voltage range 1.2 5.5 v cc v v cc = 5.5v v cc = 2.5v or 3.3v 23 45 ? 1 v reset = v wdpo = +5.5v, reset , wdpo deasserted i lkg wdpo , reset output leakage v v cc - 1.5 i source = 800?, v cc = 4.75v, reset deasserted, (max632_ _ut44, max632_ _ut46) v oh reset output voltage (max6323) 0.8 x v cc i source = 500?, v cc = 3.15v, reset deasserted (max632_ _ut23, max632_ _ut26, max632_ _ut29, max632_ _ut31) v 0.4 i sink = 100?, v cc > 1.2v, reset asserted v ol wdpo , reset output voltage 0.4 i sink = 3.2ma, v cc = 4.25v (max632_ _ut44, max632_ _ut46) 0.4 i sink = 1.2ma, v cc = 2.25v (max632_ _ut23, max632_ _ut26, max632_ _ut29, max632_ _ut31) ? 20 10mv/ms, v th +100mv to v th -100mv v cc to reset delay ms 100 180 280 reset deasserted t rp reset timeout delay v 2.25 2.32 2.38 conditions max632_ _ut23 v th reset threshold voltage max632_ _ut44 max632_ _ut46 no load, reset deasserted 2.55 2.63 2.70 max632_ _ut26 2.85 2.93 3.00 max632_ _ut29 3.00 3.08 3.15 max632_ _ut31
mr input voltage mr minimum pulse width mr glitch immunity mr to reset delay mr pullup resistance max6323/max6324 ? supervisory circuits with windowed (min/max) watchdog and manual reset _______________________________________________________________________________________ 3 conditions units min typ max symbol parameter electrical characteristics (continued) (v cc = full range, t a = -40? to +125?, unless otherwise noted. typical values are at v cc = 3v, t a = +25?.) (note 1) note 1: devices are tested at t a = +25? and guaranteed by design for t a = t min to t max , as specified. note 2: wdpo will pulse low if a falling edge is detected on wdi before this timeout period expires. note 3: to avoid a potential fake fault, the first wdi pulse after the rising edge of reset or wdpo will not create a fast watchdog timeout fault. note 4: wdpo will pulse low if no falling edge is detected on wdi after this timeout period expires. max632_aut_ _ 1 1.5 max632_but_ _ 10 15 max632_cut_ _ 10 15 max632_dut_ _ 10 15 max632_eut_ _ 10 15 max632_fut_ _ 17 23 max632_gut_ _ 29 39 watchdog timeout (fast) (notes 2, 3) max632_hut_ _ 543 719 ms t wd1 max632_aut_ _ 10 15 max632_but_ _ 100 150 max632_cut_ _ 300 450 ms max632_dut_ _ 10 15 max632_eut_ _ 60 90 s max632_fut_ _ 47 63 max632_gut_ _ 82 108 ms t wd2 max632_hut_ _ 1.3 1.8 s watchdog timeout (slow) (note 4) 300 ns wdi glitch immunity v cc = 5.5v 100 ns v ih 0.75 x v cc wdi input voltage v il 0.8 v wdi = 0 -1.5 -1 wdi input current wdi = v cc 1 1.5 ? v il = 0.8v, v ih = 0.75v x v cc 0.5 1 3 ms v ih 0.7 x v cc v il 0.3 x v cc v 1 ? v cc = 2.5v 100 ns v cc = 2.5v 120 ns 50 85 k ? minimum watchdog input pulse width watchdog input and output manual reset input wdpo pulse width
max6323/max6324 ? supervisory circuits with windowed (min/max) watchdog and manual reset 4 _______________________________________________________________________________________ 0 30 35 40 25 20 15 10 5 -40 20 0 -20 40 60 80 max6323/24-01 temperature ( c) supply current vs. temperature supply current ( a) v cc = 5.5v v cc = 3.3v v cc = 1.0v 0 30 20 5 -40 20 0 -20 40 60 80 max6323/24-02 temperature ( c) power-down reset delay ( s) power-down reset delay vs. temperature v od = 20mv v od = 100mv 25 15 10 0.9985 0.9990 0.9995 1.0000 1.0005 -40 20 0 -20 40 60 80 max6323/24-04 temperature ( c) reset threshold normalized reset threshold vs. temperature 0.9980 0.994 1.004 1.006 1.008 -40 20 0 -20 40 60 80 max6323/24-05 temperature ( c) power-up reset timeout normalized power-up reset timeout vs. temperature 1.002 1.000 0.998 0.996 0.992 1.004 1.002 1.000 0.998 1.006 1.008 -40 20 0 -20 40 60 80 max6323/24-06 temperature ( c) normalized watchdog timeout period (fast) vs. temperature normalized watchdog timeout period (fast) 0.996 0.994 0.995 1.000 1.001 0.999 0.997 0.998 0.996 1.002 1.003 -40 20 0 -20 40 60 80 max6323/24-07 temperature (?) normalized watchdog timeout period (slow) vs. temperature normalized watchdog timeout period (slow) 0.992 1.004 1.002 1.000 1.006 1.008 -40 20 0 -20 40 60 80 max6323/24-08 temperature ( c) normalized watchdog output pulse width ( s) normalized watchdog output pulse width vs. temperature 0.998 0.996 0.994 v od = v th - v cc 400 0 1 100 1000 maximum transient duration vs. reset threshold overdrive 100 50 150 200 250 300 350 max6323/24-09 reset comparator overdrive (mv) maximum transient duration ( s) 10 max632_aut23 reset asserted above this line typical operating characteristics (v cc = full range, t a = +25?, unless otherwise noted.) 40 120 100 80 60 140 160 -40 20 0 -20 40 60 80 max6323/24-03 temperature ( c) mr to reset delay (ns) mr to reset delay vs. temperature 20 0
max6323/max6324 ? supervisory circuits with windowed (min/max) watchdog and manual reset _______________________________________________________________________________________ 5 500 s/div max6323/24-10 wdi 2v/div 2v/div wdpo fast watchdog timeout period max6323aut23 5ms/div max6323/24-11 wdi 2v/div 2v/div wdpo slow watchdog timeout period max6323aut23 typical operating characteristics (continued) (v cc = full range, t a = +25?, unless otherwise noted.) pin description active-low. reset is asserted when v cc drops below v th and remains asserted until v cc rises above v th for the duration of the reset timeout period. the max6323 has a push-pull output and the max6324 has an open-drain output. connect a pullup resistor from reset to any supply voltage up to +6v. watchdog pulse output. the open-drain wdpo output is pulsed low for 1ms (typ) upon detection of a fast or slow watchdog fault. wdpo is only active when reset is high. wdpo 5 reset 6 supply voltage for the device. input for v cc reset monitor. for noisy systems, bypass v cc with a 500pf (min) capacitor. v cc 4 watchdog input. the internal watchdog timer is reset to zero and begins to count at the falling edge of wdi if reset is high. if wdi sees another falling edge within the factory-trimmed watchdog window, wdpo will remain unasserted. transitions outside this window, either faster or slower, will cause wdpo to pulse low for 1ms (typ). wdi 3 pin ground gnd 2 active-low, manual reset input. when mr is asserted low, reset is asserted low, the internal watchdog timer is reset to zero, and wdpo is reset to high impedance (open drain). after the rising edge of mr , reset is asserted for at least 100ms. leave mr unconnected or connect to v cc if unused. mr 1 function name
max6323/max6324 ? supervisory circuits with windowed (min/max) watchdog and manual reset 6 _______________________________________________________________________________________ detailed description the max6323/max6324 ? supervisory circuits main- tain system integrity by alerting the ? to fault condi- tions. in addition to a standard v cc monitor (for power-on reset, brownout detect, and power-down reset), the devices include a sophisticated watchdog timer that detects when the processor is running out- side an expected window of operation for a specific application. the watchdog signals a fault when the input pulses arrive too early (faster than the selected t wd1 timeout period) or too late (slower than the select- ed t wd2 timeout period) (figure 1). incorrect timing can lead to poor or dangerous system performance in tight- ly controlled operating environments. incorrect timing could be the result of improper ? clocking or code execution errors. if a timing error occurs, the max6323/max6324 issue a watchdog pulse output, independent from the reset output, indicating that sys- tem maintenance may be required. watchdog function a pulse on the watchdog output wdpo can be trig- gered by a fast fault or a slow fault. if the watchdog input (wdi) has two falling edges too close to each other (faster than t wd1 ) (figure 2) or falling edges that are too far apart (slower than t wd2 ) (figure 3), wdpo is pulsed low. normal watchdog operation is displayed in figure 4 ( wdpo is not asserted). the internal watch- dog timer is cleared when a wdi falling edge is detect- ed within the valid watchdog window or when the device? reset or wdpo outputs are deasserted. all wdi input pulses are ignored while either reset or wdpo is asserted. figure 1 identifies the input timing regions where wdpo fault outputs will be observed with respect to t wd1 and t wd2 . after reset or wdpo deasserts, the first wdi falling edge is ignored for the fast fault condition (figure 2). upon detecting a watchdog fault, the wdpo output will pulse low for 1ms. wdpo is an open-drain output. connect a pullup resistor on wdpo to any supply up to +6v. v cc reset the max6323/max6324 also include a standard v cc reset monitor to ensure that the ? is started in a known state and to prevent code execution errors during power-up, power-down, or brownout conditions. reset is asserted whenever the v cc supply voltage * undetermined states may or may not generate a fault condition. possible states guaranteed to assert wdpo guaranteed to assert wdpo guaranteed not to assert wdpo fast fault condition 1 slow fault condition 3 normal operation condition 2 t wd1 (min) ) t wd1 (max) t wd2 (min) t wd2 (max) * undetermined * undetermined figure 1. detailed watchdog input timing relationship
max6323/max6324 ? supervisory circuits with windowed (min/max) watchdog and manual reset _______________________________________________________________________________________ 7 reset wdpo wdi fast fault t wdi < t wd1 (min) figure 2. fast fault timing reset wdpo wdi slow fault t wdi < t wd2 (max) figure 3. slow fault timing reset wdpo wdi normal operation (no pulsing, output stays high) t wd1 (max) < t wdi < t wd2 (min) h l figure 4. normal operation, wdpo not asserted
max6323/max6324 falls below the preset threshold or when the manual reset input ( mr) is asserted. the reset output remains asserted for at least 100ms after v cc has risen above the reset threshold and mr is deasserted (figure 5). for noisy environments, bybass v cc with a 500pf (min) capacitor to ensure correct operation. the max6323 has a push-pull output stage, and the max6324 utilizes an open-drain output. connect a pull- up resistor on the reset output of the max6324 to any supply up to +6v. select a resistor value large enough to register a logic low (see electrical characteristics ) and small enough to register a logic high while supply- ing all input leakage currents and leakage paths con- nected to the reset line. a 10k ? pullup is sufficient in most applications. manual reset input many ?-based products require manual reset capabil- ity to allow an operator or external logic circuitry to initi- ate a reset. the manual reset input ( mr ) can connect directly to a switch without an external pullup resistor or debouncing network. mr is internally pulled up to v cc and, therefore, can be left unconnected if unused. mr is designed to reject fast, negative-going transients (typically 100ns pulses), and it must be held low for a minimum of 1? to assert the reset output (figure 5). a 0.1? capacitor from mr to ground provides additional noise immunity. after mr transitions from low to high, reset will remain asserted for the duration of the reset timeout period, at least 100ms. applications information negative-going v cc transients the max6323/max6324 are relatively immune to short- duration negative-going v cc transients (glitches), which usually do not require the entire system to shut down. typically, 200ns large-amplitude pulses (from ground to v cc ) on the supply will not cause a reset. lower amplitude pulses result in greater immunity. typically, a v cc transient that falls 100mv below the reset threshold and lasts less than 20? will not trigger a reset (see typical operating characteristics ). an optional 0.1? bypass capacitor mounted close to v cc provides additional transient immunity. ensuring a valid reset output down to v cc = 0 when v cc falls below + 1.2v, the max6323 reset out- put no longer sinks current; it becomes an open circuit. therefore, high-impedance cmos logic inputs con- nected to reset can drift to undetermined voltages. this does not present a problem in most applications, since most ?s and other circuitry are inoperative with v cc below + 1.2v. however, in applications where reset must be valid down to 0, adding a pulldown resistor to reset causes any stray leakage currents to flow to ground, holding reset low (figure 6). r1? value is not critical; 100k ? is large enough not to load reset and small enough to pull reset to ground. this scheme does not work with the open-drain output of the max6324. ? supervisory circuits with windowed (min/max) watchdog and manual reset 8 _______________________________________________________________________________________ mr reset v cc v th 100ms (min) 120ns (typ) 20 s (typ) 1 s (min) 100ms (min) figure 5. reset timing relationship
interfacing to ?s with bidirectional reset pins since the reset output on the max6324 is open-drain, this device easily interfaces with ?s that have bidirec- tional reset pins, such as the motorola 68hc11. connecting the ? supervisor? reset output directly to the microcontroller? (??) reset pin with a single pullup resistor allows either device to assert reset (figure 7). max6324 open-drain reset output allows use with multiple supplies generally, the pullup resistor connected to the max6324 will connect to the supply voltage that is being monitored at the ic? v cc pin. however, some systems may use the open-drain output to level-shift from the monitored supply to reset circuitry powered by some other supply (figure 8). keep in mind that as the max6324? v cc decreases below + 1.2v, so does the ic? ability to sink current at reset. also, with any pull- up resistor, reset will be pulled high as v cc decays toward 0. the voltage where this occurs depends on the pullup resistor value and the voltage to which it is connected. watchdog software considerations to help the watchdog timer monitor software execution more closely, set and reset the watchdog input at dif- ferent points in the program, rather than ?ulsing?the watchdog input high-low-high or low-high-low. this technique avoids a ?tuck?loop in which the watchdog time would continue to be reset within the loop, keeping the watchdog from timing out. figure 9 shows an example of a flow diagram where the i/o driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. if the program should ?ang?in any subroutine, the problem would be quickly corrected, since the i/o is continually set low and the watchdog time is allowed to time out, causing a reset or interrupt to be issued. wdpo to mr loopback an error detected by the watchdog often indicates that a problem has occurred in the ? code execution. this could be a stalled instruction or a loop from which the processor cannot free itself. if the ? will still respond to a nonmaskable input (nmi), the processor can be redi- rected to the proper code sequence by connecting the wdpo output to an nmi input. internal ram data should not be lost, but it may have been contaminated by the same error that caused the watchdog to time out. if the processor will not recognize nmi inputs, or if the internal data is considered potentially corrupted when a watchdog error occurs, the processor should be restarted with a reset function. to obtain proper reset timing characteristics, the wdpo output should be con- nected to the mr input, and the reset output should max6323/max6324 ? supervisory circuits with windowed (min/max) watchdog and manual reset _______________________________________________________________________________________ 9 max6323 gnd v cc v cc reset r1 100k figure 6. reset valid to v cc = ground circuit max6324 gnd gnd v cc v cc v cc p reset reset input figure 7. interfacing to ?s with bidirectional reset pins
max6323/max6324 drive the ? reset input (figure 10). the short 1ms wdpo pulse output will assert the manual reset input and force the reset output to assert for the full reset timeout period (100ms min). all internal ram data is lost during the reset period, but the processor is guar- anteed to begin in the proper operating state. ? supervisory circuits with windowed (min/max) watchdog and manual reset 10 ______________________________________________________________________________________ start set wdi low subroutine or program loop set wdi high return end figure 9. watchdog flow diagram max6324 gnd gnd v cc +3.3v +5.0v v cc 5v system reset reset input r pullup figure 8. max6324 open-drain reset output allows use with multiple supplies chip information transistor count: 1371 process: bicmos suffix 46 44 31 29 26 23 min max units v 4.75 4.50 3.15 3.00 2.70 2.38 2.32 2.63 2.93 3.08 4.38 4.63 typ 4.50 4.25 3.00 2.85 2.55 2.25 max6323aut29 max6324aut29 max6323aut46 max6324aut46 max6323cut29 max6324but29 max6323cut46 max6324but46 max6323dut29 max6324eut29 max6323dut46 max6324eut46 max6323hut29 max6324hut29 max6323hut46 max6324hut46 reset threshold range (-40? to +125?) standard versions
max6323/max6324 ? supervisory circuits with windowed (min/max) watchdog and manual reset ______________________________________________________________________________________ 11 max6323 max6324 reset wdpo p reset *max6324 only mr wdi i/o gnd v cc v cc v cc *r pullup 500pf figure 10. wdpo to mr loopback circuit max6323 max6324 reset wdpo nmi p reset *max6324 only mr wdi i/o gnd v cc v cc v cc *r pullup 500pf typical operating circuit
max6323/max6324 ? supervisory circuits with windowed (min/max) watchdog and manual reset maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information 6lsot.eps max6323/max6324

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